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350 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 description the pi6c133, a low-skew, low-jitter 133 mhz clock generator, is specifically designed to meet all the clocking requirements for 133 mhz and 100 mhz desktops with high-performance and lower-power features. split power supplies of 2.5v and 3.3v are used to reduce power consumption, minimize noise and to ensure cpu independence. the 2.5v supply is used to power cpuclk clocks to the processor module. 2.5v signalling is compliant to jedec standard 8-x. the rest of the circuitry is powered by a 3.3v supply. key features, such as power-management and spread-spectrum functions, are fully supported. pwrdwn# signal will turn off all internal circuits and keep all outputs to a low state, making the power consumption less than 100 m a. for less stringent power requirements, cpustop# will turn off cpuclk and 3v66 outputs instantane ously. spread spectrum function can be optionally disabled by pulling spread# pin to a high state. features ? four copies of cpu clock @ 133/100 mhz ? eight copies of pci clock (synchronous w/cpu clock) including one free running pci clock. ? two copies of fixed frequencies 3.3v clock @ 66 mhz ? three copies of apic clock @ 16.667 mhz, synchronous to cpu clock ? one copy of 48 mhz clock ? two copies of ref. clock @ 14.13818 mhz ? ref.14.31818 mhz xtal oscillator input ? cpu clock frequency selection pin for selecting 133 mhz or 100 mhz operation ? power management control input pins ? supports reliance (rcc) chip set ? spread spectrum enable/disable pin ? 56-pin ssop (v) package block diagram pin configuration 133 mhz c lock generation for pentium ii/iii processors pciclk[1:7] cpuclk[0:3] ref[0:1] 2 apic[0:2] ref osc 4 48mhz pcistop# cpustop# div pll1 pciclk_f 2 7 3v66mhz pll2 sel0,1 spread# xtal_out xtal_in 3 sel100/33# pwrdwn# div v ss 1 ref0 2 ref1 3 v dd 3v 4 xtal_in 5 xtal_out 6 v ss 7 pciclk_f 8 pciclk1 9 v dd 3v 10 pciclk2 11 pciclk3 12 v ss 13 pciclk4 14 pciclk5 15 v dd 3v 16 pciclk6 17 pciclk7 18 v ss 19 v ss 20 3v66_0 21 3v66_1 22 v dd 3v 23 v ss 24 v dd 2v apic2 apic1 apic0 v ss v dd 2v nc nc v ss 56 v dd 2v 55 cpuclk3 54 cpuclk2 53 v ss 52 v dd 2v 51 cpuclk1 cpuclk0 50 49 v ss 48 v dd 3v 2.5v supply 47 v ss 46 pcistop# 45 cpustop# 44 pwrdwn# 43 spread# 42 sel1 41 40 39 38 37 36 35 34 33 nc 25 nc 26 v dd 3v 27 sel133/100# 28 sel0 v dd 3v 48mhz v ss 32 31 30 29 56-pin v
351 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors pin description n i pl o b m y so / in o i t p i r c s e d l a n o i t c n u f 3 , 2] 1 : 0 [ f e ro t u p t u o k c o l c z h m 8 1 3 . 4 1 v 3 . 3 5n i _ l a t xi t u p n i l a t s y r c z h m 8 1 3 . 4 1 6t u o _ l a t xo t u p t u o l a t s y r c z h m 8 1 3 . 4 1 8f _ k l c i c po k c o l c i c p g n i n n u r e e r f v 3 . 3 8 1 , 7 1 , 5 1 , 4 1 , 2 1 , 1 1 , 9] 7 - 1 [ k l c i c po s t u p t u o k c o l c i c p v 3 . 3 2 2 , 1 2] 1 - 0 [ 6 6 v 3o s t u p t u o k c o l c z h m 6 6 d e x i f v 3 . 3 8 2# 0 0 1 / 3 3 1 l e si . s t u p t u o u p c z h m 0 0 1 r o z h m 3 3 1 r o f t u p n i e l b i t a p m o c l t t v l 3 . 3 z h m 0 0 1 = l z h m 3 3 1 = h 0 3z h m 8 4o t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 3 3 , 2 3] 1 - 0 [ l e si n o i t c n u f n o i t c e l e s c i g o l r o f t u p n i e l b i t a p m o c l t t v l 3 . 3 4 3# d a e r p si w o l d l e h n e h w e d o m m u r t c e p s d a e r p s s e l b a n e . t u p n i e l b i t a p m o c l t t v l 3 . 3 5 3# n w d r w pi w o l d l e h n e h w e d o m n w o d r e w o p s r e t n e e c i v e d . t u p n i e l b i t a p m o c l t t v l 3 . 3 6 3# p o t s u p ci s k c o l c 6 6 v 3 d n a k l c u p c l l a s p o t s . t u p n i e l b i t a p m o c l t t v l 3 . 3 . w o l d l e h n e h w 7 3# p o t s i c pi f _ k l c i c p t p e c x e s k c o l c i c p l l a s p o t s . t u p n i e l b i t a p m o c l t t v l 3 . 3 . w o l d l e h n e h w 6 4 , 5 4 , 2 4 , 1 4] 3 - 0 [ k l c u p co f o e t a t s n o g n i d n e p e d z h m 0 0 1 r o z h m 3 3 1 . t u p t u o k c o l c s u b t s o h v 5 . 2 . # 0 0 1 / 3 3 1 l e s 5 5 , 4 5 , 3 5] 2 - 0 [ c i p ao u p c e h t h t i w s u o n o h c n y s e d i v i d g n i n n u r s t u p t u o k c o l c v 5 . 2 . t i m i l z h m 7 6 . 6 1 d e x i f . y c n e u q e r f k c o l c ) s u b t s o h ( 8 / u p c = c i p a , z h m 3 3 1 = u p c f i 6 / u p c = c i p a , z h m 0 0 1 = u p c f i 9 3 , 1 3 , 7 2 , 3 2 , 6 1 , 0 1 , 4v d d v 3 v 3 . 3 r e w o p y l p p u s r e w o p v 3 . 3 9 2 , 4 2 , 0 2 , 9 1 , 3 1 , 7 , 1 2 5 , 8 4 , 4 4 , 0 4 , 8 3 v s s v s s d n u o r g 6 5 , 1 5 , 7 4 , 3 4v d d v 2 v 5 . 2 r e w o p r e w o p v 5 . 2 0 5 , 9 4 , 6 2 , 5 2c nd e s u n u
352 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors pi6c133-03 select functions pi6c133-03 truth table notes: 1. required for board-level ?bed of nails? testing. 2. 48 mhz pll disabled to reduce component jitter. 48 mhz outputs are held h-z instead of driven to a low state. 3. ?normal? mode of operation. 4. tclk is a test clock over driven on the xtal_in input during test mode. tclk mode is based on 133 mhz cpu select logic. 5. for dc output impedance verification. 6. range of reference frequency allowed is min = 14.316 nominal = 14.31818 mhz, max = 14.32 mhz. 7. frequency accuracy of 48 mhz must be +167ppm to match usb default. apic and pci clock outputs must be synchronous with cpuclk pciclk outputs tracks cpuclk very closely. the cpuclks lead the pciclks by 1.5 - 4.0ns with assuming they are fully loaded wit h the appropriate loads. the frequency of pciclk is fixed at 33.33mhz. pciclk is cpuclk divided by four @ 133.33mhz, or cpuclk divided by three @100.0 mhz. apic clocks are now synchronous with the cpuclk outputs. the ioapic voltage will track that of the host bus and will have max imum frequency of 16.67 mhz. apic clocks will be derived by dividing the cpuclk outputs by eight when the host bus is 133.33 mhz, an d by six when the host bus is 100 mhz. apic clocks will lag the host bus clocks by 1.5 - 4.0ns at the maximum device load of 20pf . # 0 0 1 / 3 3 1 l e s1 l e s0 l e sn o i t c n u f 000 e t a t s - i r t s t u p t u o l l a 001 ) d e v r e s e r ( 010 e v i t c a n i l l p z h m 8 4 , z h m 0 0 1 e v i t c a 011 e v i t c a l l p z h m 8 4 , z h m 0 0 1 e v i t c a 100 e d o m t s e t 101 ) d e v r e s e r ( 110 e v i t c a n i l l p z h m 8 4 , z h m 3 3 1 e v i t c a 111 e v i t c a l l p z h m 8 4 , z h m 3 3 1 e v i t c a l e s # 0 0 1 / 3 3 1 1 l e s0 l e su p c6 6 v 3i c pz h m 8 4f e rc i p as e t o n 000 z - i hz - i hz - i hz - i hz - i hz - i h1 001 a / na / na / na / na / na / n 010 z h m 0 0 1z h m 6 6z h m 3 3z - i hz h m 8 1 3 . 4 1z h m 7 6 . 6 12 011 z h m 0 0 1z h m 6 6z h m 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 7 6 . 6 17 , 6 , 3 100 2 / k l c t4 / k l c t8 / k l c t2 / k l c tk l c t6 1 / k l c t5 , 4 101 a / na / na / na / na / na / n 110 z h m 3 3 1z h m 6 6z h m 3 3z - i hz h m 8 1 3 . 4 1z h m 7 6 . 6 12 111 z h m 3 3 1z h m 6 6z h m 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 7 6 . 6 17 , 6 , 3
353 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors notes: 1. low means outputs held static low as per latency requirement below. 2. on means active. 3. pwrdwn# pulled low, impacts all outputs including ref and 48 mhz outputs. 4. all 3v66 as well as all cpu clocks should stop cleanly when cpustop# is pulled low. 5. apic, ref, 48 mhz signals are not controlled by the cpustop# functionality and are enabled all in all conditions except pwrdwn# = low. v dd 3v power-down removal the pi6c133-03 device meets the following requirement to allow for a common design across multiple platforms. to allow for multiple devices in platforms to share voltage regula- tors, the pi6c133-03 allows the removal of power from the v dd 3v voltage pins during the following specific condition. (leakage currents from the v dd 3v and v dd 2v pins are not allowed to violate existing powerdown# specifications.) going to powerdown mode: 1. assert the pwrdwn# signal to the pi6c133-03. 2. remove power from the 3.3v pins of the pi6c133-03. 3. all input pins of pi6c133-03 will be either powered down or driven to ground. 4. v dd 3 power plane will be pulled to or discharge to < 250mv. 5. the 2.5v pins will remain powered at 2.5v. to restore power: 1. apply 3.3v to the pi6c133-03. 2. wait 200-2000ms. 3. de-assert the pwrdwn# signal. 4. wait 1ms longer than lock time specified for the device. 5. continue operation as normal pi6c133-03 clock enable configuration # p o t s u p c# n w d r w p# p o t s i c pk l c u p cc i p a6 6 v 3i c pf _ i c pz h m 8 4 , f e rc s os o c v x0xw o lw o lw o lw o lw o lw o lf f of f o 010w o ln ow o lw o ln on on on o 011w o ln ow o ln on on on on o 110n on on ow o ln on on on o 111n on on on on on on on o the power-down controller provides a signal that is latched with its own copy of the pci clock. clock sequencing always guarantees full clock timing parameters after the system has initially powered up, except where noted. during power-up and power-down operations using the pwrdwn# select pin, partial clocks are not allowed and all clock timing parameters are met except for the following: the first clock pulse coming out of a stopped clock condition could be slightly distorted because of the other clock network charging requirements: it is also understood that board routing and signal loading have a large impact on the initial clock distortion.
354 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors cpustop# is an input to the clock synthesizer. it is used to turn off the cpu and 3v66 clocks for low power operation. cpustop# is asserted asynchronously by the external clock control logic with the rising edge of the free running pci clock (and hence c pu clock) and must be internally synchronized to the external pci_f output. all other clocks will continue to run while the cpu clocks ar e disabled. the cpu clocks must always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse. only one rising edge of the pci_f is allowed after the clock control logic switched for both the cpu and 3v66 outputs to become enabled/disabled. pi6c133-03 cpustop# timing diagram notes: 1. all internal timing is referenced to the cpuclk 2. the internal label means inside the chip and is a reference only. this in fact may not be the way that the control is designe d. 3. cpustop# signal is an input signal that must be made synchronous to free running pci_f 4. 3v66 clocks also stop/start before 5. pwrdwn# and pcistop# are shown in a high state. 6. diagrams shown with respect to 133 mhz. similar operation when cpu is 100 mhz. pi6c133-03 power management requirements notes: 1. clock on/off latency is defined in the number of rising edges of free running pciclks between the clock disable goes low/high to the first valid clock comes out of the device. 2. power up latency is when pwrdwn# goes inactve (high) to when the first valid clocks are driven from the device. l a n g i se t a t s l a n g i s y c n e t a l k l c i c p f o s e g d e g n i s i r f o . o n # p o t s u p c ) d e l b a s i d ( 01 ) d e l b a n e ( 11 # p o t s i c p ) d e l b a s i d ( 01 ) d e l b a n e ( 11 # n w d r w p ) n o i t a r e p o l a m r o n ( 1s m 3 ) n w o d r e w o p ( 0. x a m 2 cpuclk cpustop# pcistop#=h pwrdwn#=h pci_ref cpuclk (internal) pciclk (internal) (external) (external) 3v66 (external)
355 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors the power-down selection is used to put the part into a very low power state without turning off the power to the part. pwrdwn# is an asynchronous active low input. the signal needs to be synchronized internal to the device prior to powering down the clock synt hesizer. pwrdwn# is an asynchronous function for powering up the system. internal clocks are not running after the device is put in powe r down. when pwrdwn# is active low all clocks need to be driven to a low value and held prior to turning off the vco?s and the crystal. the power-up latency is less than 3ms. the power-down latency is short and conforms to the sequence requirements shown below. pcist op# and cpustop# are considered to be don?t cares during power-down operations. ref and 48 mhz clocks are expected to be stopped in the low state as soon as possible. owing to the state of internal logic stopping and holding ref clock outputs in the low s tate, more than one clock cycle may be required to complete. pcistop# is an input to the clock synthesizer and is made synchronous to the clock driver pci_f output. it is used to turn off the pci clocks for low-power operation. pci clocks are required to be stopped in a low state and started such that a full high pulse width is guaranteed. only one rising edge of pci_f is needed after the clock control logic switched for the pci outputs to become enabled/disabled. notes: 1. all internal timing is referenced to the cpuclk 2. pcistop# signal is an input signal which is made synchronous to pci_f output. 3. internal means inside the chip. 4. all other clocks continue to run undisturbed. 5. pwrdwn# and cpustop# are shown in a high state. 6. diagrams shown with respect to 133 mhz. similar operation when cpu is 100 mhz. pi6c133-03 pcistop# timing diagram notes: 1. all internal timing is referenced to the cpuclk 2. internal means inside the chip. 3. pwrdwn# is an asynchronous input and metstable conditions could exist. this signal is required to be synchronized inside the part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133 mhz. similar operation when cpu is 100 mhz. pi6c133-03 pwrdwn# timing diagram cpuclk pciclk cpustop#=h pcistop# pwrdwn#=h pciclk_f pciclk (internal) (internal) (external) (external) cpuclk (internal) pciclk (internal) vco pwrdwn# cpuclk (external) pciclk (external) crystal
356 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors dc specifications dc parameters must be sustainable under steady state (dc) conditions absolute maximum dc power supply l o b m y sr e t e m a r a p. n i m. x a ms t i n u v 3 d d v v 2 d d v e g a t l o v y l p p u s5 . 0 -6 . 4v t s e r u t a r e p m e t e g a r o t s5 6 -0 5 1c o l o b m y sr e t e m a r a p. n i m. x a ms t i n u v 3 h i ) 1 ( e g a t l o v h g i h t u p n i v 3 . 35 . 0 -6 . 4 v v 3 l i e g a t l o v w o l t u p n i v 3 . 35 . 0 - . t o r p d s e ) 2 ( n o i t c e t o r p d s e t u p n i0 0 0 2 absolute maximum dc i/o notes: 1. maximum v ih is not to exceed maximum v dd . 2. human body model. l o b m y sr e t e m a r a pn o i t i d n o c. n i m. x a ms t i n u v 3 d d ve g a t l o v y l p p u s 3 . 3 ) 4 ( % 5 v 3 . 35 3 1 . 35 6 4 . 3 v v 2 d d ve g a t l o v y l p p u s v 5 . 2 ) 4 ( % 5 v 5 . 25 7 3 . 25 2 6 . 2 % 5 v 3 . 3 = v 3 d d v v 3 h i e g a t l o v h g i h t u p n i v 3 . 3 ) 7 ( d d v3 0 . 2d d v3 . 0 + v v 3 l i e g a t l o v w o l t u p n i v 3 . 3 ) 7 ( v s s 3 . 0 ?8 . 0 i l i t n e r r u c e g a k a e l t u p n i ) 7 , 3 ( v < 0 n i 357 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors buffer specifications e m a n r e f f u bv c c ) v ( e g n a r e c n a d e p m i ) s m h o ( e p y t r e f f u b c i p a , u p c5 2 6 . 2 - 5 7 3 . 25 4 - 5 . 3 11 e p y t f e r , z h m 8 45 6 4 . 3 - 5 3 1 . 30 6 - 0 23 e p y t 6 6 v 3 , i c p5 6 4 . 3 - 5 3 1 . 35 5 - 2 15 e p y t l o b m y sr e t e m a r a pn o i t i d n o c. n i m. x a ms t i n u v v 3 d d % 5 v 3 . 3 = v h o p e g a t l o v h g i h t u p t u o s u b i c p ) 1 ( i h o a m 1 - =4 . 2 v v l o p e g a t l o v w o l t u p t u o s u b i c p ) 4 , 1 ( i l o a m 1 =5 5 . 0 c n i e c n a t i c a p a c n i p t u p n i5 f p c l a t x e c n a t i c a p a c n i p l a t x ) 5 ( 5 . 3 15 . 2 2 c t u o e c n a t i c a p a c n i p t u p t u o6 l n i p e c n a t c u d n i n i p7h n t a e r u t a r e p m e t t n e i b m aw o l f r i a o n00 7c o notes: 1. signal edge is required to be monotonic when transitioning through this region. 2. input leakage current does not include inputs with pull-up or pull-down resistors. 3. no power sequencing is implied or allowed to be required in the system. 4. conforms to 5v pci signaling specification. 5. as seen by the crystal. device is intended to be used with a 17-20pf at crystal. 6. all inputs referenced to 3.3v power supply. dc operating requirements (continued)
358 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors l o b m y sr e t e m a r a pn o i t i d n o c. n i m. p y t. x a ms t i n u i n i m h o t n e r r u c p u - l l u p ) 1 ( v t u o v 0 . 1 =9 2 ? a m i x a m h o t n e r r u c p u - l l u p ) 1 ( v t u o v 5 3 1 . 3 =3 2 ? i n i m l o t n e r r u c n w o d - l l u p ) 1 ( v t u o v 5 9 . 1 =9 2 i x a m l o t n e r r u c n w o d - l l u p ) 1 ( v t u o v 4 . 0 =7 2 t h r 3 e p y t v 3 . 3 e t a r e g d e e s i r t u p t u o ) 2 ( % 5 v 3 . 3 v 4 . 2 ? v 4 . 0 @ 5 . 00 . 2 s n / v t h f v 3 . 33 e p y t e t a r e g d e l l a f t u p t u o ) 2 ( % 5 v 3 . 3 v 4 . 0 ? 4 . 2 @ 5 . 00 . 2 notes: 1. production testing is expected to be a subset of characterization testing. 2. output rise and fall time. 3. reciever logic thresholds are v il = 0.7 and v ih = 1.7v 4. r on 13.5-45 ohm with a 29 ohm nominal driver impedance. 5. r on = v out /i oh , v out /i ol measured at v cc /2. type 3 buffer characteristics operating requirements notes: 1. production testing is expected to be a subset of characterization testing. 2. output rise and fall time. 3. receiver logic thresholds are v il = 0.8 and v ih = 2.0v. 4. r on 20 -60 ohm with a 40 ohm nominal driver impedance. 5. r on = v out /i oh ,v out /i ol measured at v cc /2. l o b m y sr e t e m a r a pn o i t i d n o c. n i m. p y t. x a ms t i n u i n i m h o t n e r r u c p u - l l u p ) 1 ( v t u o v 0 . 1 =7 2 ? a m i x a m h o t n e r r u c p u - l l u p ) 1 ( v t u o v 5 7 3 . 2 =7 2 ? i n i m l o t n e r r u c n w o d - l l u p ) 1 ( v t u o v 2 . 1 =7 2 i x a m l o t n e r r u c n w o d - l l u p ) 1 ( v t u o v 3 . 0 =0 3 t h r 1 e p y t v 5 . 2e t a r e g d e e s i r t u p t u o ) 2 ( % 5 v 5 . 2 v 0 . 2 ? v 4 . 0 @ 1 / 11 / 4 s n / v t h f 1 e p y t v 5 . 2e t a r e g d e l l a f t u p t u o ) 2 ( % 5 v 5 . 2 v 4 . 0 ? v 0 . 2 @ 1 / 11 / 4 type 1 buffer characteristics operating requirements
359 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors type 5 buffer characteristics operating requirements notes: 1. production testing is expected to be a subset of characterization testing. 2. output rise and fall time. 3. output rise and fall time must be guaranteed across v cc , process and temperature range. 4. receiver logic thresholds are v il = 0.8 and v ih = 2.0 volts 5. r on 12 -55 ohm with a 30 ohm nominal driver impedance. 6. r on = v out /i oh , v out /i ol measured at v cc /2. 7. see pci specification for additional pci details l o b m y sr e t e m a r a pn o i t i d n o c. n i m. p y t. x a ms t i n u i n i m h o t n e r r u c p u - l l u p ) 1 ( v t u o v 0 . 1 =3 3 ? a m i x a m h o t n e r r u c p u - l l u p ) 1 ( v t u o v 5 3 1 . 3 =3 3 ? i n i m l o t n e r r u c n w o d - l l u p ) 1 ( v t u o v 5 9 . 1 =0 3 i x a m l o t n e r r u c n w o d - l l u p ) 1 ( v t u o v 4 . 0 =8 3 t h r 4 e p y t v 3 . 3 e t a r e g d e e s i r t u p t u o ) 2 ( % 5 v 3 . 3 v 4 . 2 ? v 4 . 0 @ 1 / 1 1 / 4s n / v t h f 4 e p y t v 3 . 3 e t a r e g d e l l a f t u p t u o ) 2 ( % 5 v 3 . 3 v 4 . 0 ? v 4 . 2 @ 1 / 1
360 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors ac timing host bus ac timing requirements l o b m y sr e t e m a r a p t s o h z h m 3 3 1t s o h z h m 0 0 1 s t i n u . n i m. x a m. n i m. x a m d o i r e p td o i r e p k l c u p c / t s o h ) 8 , 1 ( 5 . 70 . 80 . 0 15 . 0 1 s n t h g i h e m i t h g i h k l c u p c / t s o h ) 9 , 4 ( 7 8 . 1a / n0 . 3a / n t w o l e m i t w o l k l c u p c / t s o h ) 9 , 5 ( 7 6 . 1a / n8 . 2a / n t e s i r e m i t e s i r k l c u p c / t s o h ) 7 ( 4 . 06 . 14 . 06 . 1 t l l a f e m i t l l a f k l c u p c / t s o h ) 7 ( 4 . 06 . 14 . 06 . 1 d o i r e p td o i r e p k l c c i p a ) 8 , 1 ( 0 . 0 60 . 4 60 . 0 60 . 4 6 s n t h g i h e m i t h g i h k l c c i p a ) 9 , 4 ( 5 . 5 2a / n5 . 5 2a / n t w o l e m i t w o l k l c c i p a ) 9 , 5 ( 3 . 5 2a / n3 . 5 2a / n t e s i r e m i t e s i r k l c c i p a ) 7 ( 4 . 06 . 14 . 06 . 1 t l l a f e m i t l l a f k l c c i p a ) 7 ( 4 . 06 . 14 . 06 . 1 d o i r e p td o i r e p k l c 6 6 v 3 ) 8 , 3 , 1 ( 0 . 5 10 . 6 10 . 5 10 . 6 1 s n t h g i h e m i t h g i h k l c 6 6 v 3 ) 9 , 4 ( 5 2 . 5a / n5 2 . 5a / n t w o l e m i t w o l k l c 6 6 v 3 ) 9 , 5 ( 5 0 . 5a / n5 0 . 5a / n t e s i r e m i t e s i r k l c 6 6 v 3 ) 7 ( 4 . 06 . 14 . 06 . 1 t l l a f e m i t l l a f k l c 6 6 v 3 ) 7 ( 4 . 06 . 14 . 06 . 1 d o i r e p td o i r e p k l c i c p ) 8 , 2 , 1 ( 0 . 0 3a / n0 . 0 3a / n s n t h g i h e m i t h g i h k l c i c p ) 9 , 4 ( 0 . 2 1a / n0 . 2 1a / n t w o l e m i t w o l k l c i c p ) 9 , 5 ( 0 . 2 1a / n0 . 2 1a / n t e s i r e m i t e s i r k l c i c p ) 7 ( 5 . 00 . 25 . 00 . 2 t l l a f e m i t l l a f k l c i c p ) 7 ( 5 . 00 . 25 . 00 . 2 h z p t , l z p t) s t u p t u o l l a ( y a l e d e l b a n e t u p t u o0 . 10 . 0 10 . 10 . 0 1 s n h z p t , z l p t) s t u p t u o l l a ( y a l e d e l b a s i d t u p t u o0 . 10 . 0 10 . 10 . 0 1 e l b a t s t m o r f n o i t a z i l i b a t s k c o l c l l a p u - r e w o p ) 6 ( 33s m
361 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors notes: 1. period, jitter, offset and skew measured on rising edge @1.25v for 2.5v clocks and @1.5v for 3.3v clocks. 2. the pciclk clock is the host clock divided by four at host = 133 mhz. 3v66 clock internal vco frequency divided by three for host = 100 mhz 3. 3v66 is internal vco frequency divided by four for host = 133 mhz. 3v66 clock is internal vco frequency divided by three for host = 100 mhz 4. t high is measured at 2.0v for 2.5v outputs, 2.4v for 3.3v outputs. 5. t low is measured at 0.4v for all outputs. 6. the time specified is measured from when v ddq achieves its nominal operating level (typical condition v ddq = 3.3v) until the frequency output is stable and operating with in specification. 7. t rise and t fall are measured as a transition through the threshold region v ol = 0.4v and v oh = 2.0v (1ma) jedec specification. 8. the average period over any 1 m s period of time is greater than the minimum specified period. 9. calculated at minimum edge rate(1v/ns) to guarantee 45/55% duty-cycle. pulsewidth is required to be wider at faster edge-rate to ensure duty cycle specification is met. p u o r g t u p t u o n i p - n i p w e k s e l c y c - e l c y c r e t t i j e l c y c y t u dm o nd d v r e t t i j , w e k s t n i o p e r u s a e m u p cs p 5 7 1s p 0 5 15 5 / 5 4 v 5 . 2v 5 2 . 1 c i p as p 0 0 5s p 0 5 25 5 / 5 4 z h m 8 4a / ns p 0 0 55 5 / 5 4 v 3 . 3v 5 . 1 6 6 v 3s p 0 5 2s p 0 0 55 5 / 5 4 i c ps p 0 0 5s p 0 0 55 5 / 5 4 f e ra / ns p 0 0 0 15 5 / 5 4 group skew and jitter limits p u o r gt e s f f o) d e p m u l ( s d a o l t n e m e r u s a e ms t n i o p e r u s a e m 6 6 v 3 o t u p cs d a e l u p c s n 5 . 1 - 0 . 0f p 0 3 @ 6 6 v 3 , f p 0 2 @ u p cv 5 . 1 @ 6 6 v 3 , v 5 2 . 1 @ u p c i c p o t u p cs d a e l u p c s n 0 . 4 - 5 . 1f p 0 3 @ u p c , f p 0 3 @ 6 6 v 3v 5 . 1 @ i c p , v 5 . 1 @ 6 6 v 3 c i p a o t u p cs d a e l u p c s n 0 . 4 - 5 . 1f p 0 2 @ c i p a , f p 0 2 @ u p cv 5 . 1 @ c i p a , v 5 2 . 1 @ u p c notes: 1. all offsets are to be measured at rising edges only offset specifications listed above are guaranteed/tested. the specification is treated as any ouput within the first specified bank to any output of the specified bank. pin-pin skew is implied within offset specification, jitter is not. previous offset specifications such as cpu to pci offset are no longer required. group offset limits
362 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors group offset waveforms test and measurement minimum and maximum lumped capacitive test loads notes: 1. maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer. 2. minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer. 3. rise/fall times are specified with pure capacitative load as shown. testing may be done with an additional 500 w resistor in parallel, if properly correlated with the capacitive load. k c o l cd a o l . n i md a o l . x a ms t i n us e t o n k l c u p c 0 1 0 2f ps d a o l 2 e l b i s s o p , d a o l e c i v e d 1 k l c i c p0 3s t n e m e r i u q e r 1 . 2 i c p t e e m t s u m 6 6 v 30 3s d a o l 2 e l b i s s o p , d a o l e c i v e d 1 k c o l c z h m 8 40 2d a o l e c i v e d 1 f e r0 2d a o l e c i v e d 1 c i p a0 2d a o l e c i v e d 1 1.25v cpu leads 3v66 cpu leads pci 1.5v cpu@133 mhz 3v66@66 mhz 1.5v 1.5v cpu@133 mhz pci@33 mhz 1.25v 1.25v cpu@133 mhz apic@16.6 mhz cpu leads apic
363 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors pi6c133-03 clock waveforms pi6c133-03 component versus system measure points 2.0 1.25 0.4 t rise t fall t low duty cycle tperiod thigh 2.5v clocking interface test load output buffer test point clock output waveform 2.4 1.5 0.4 t rise t fall t low duty cycle tperiod thigh 3.3v clocking interface v oh = 2.0v v ih = 1.7v 1.25v v il = 0.7v vdd2v 2.5 volt measure points v ss v ol = 0.4v measurement points for system-level inputs measurement points for component output v oh = 2.4v v ih = 2.0v 1.5v v il = 0.8v vdd3v 3.3 volt measure points v ss v ol = 0.4v measurement points for system level inputs measurement points for component output
364 ps8415 07/23/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c133-03 133 mhz clock generation for pentium ii/iii processors r e b m u n n i pn o i t p i r c s e d v 3 0 - 3 3 1 c 6 i pe g a k c a p p o s s n i p - 6 5 56-pin ssop package data ordering information pericom semiconductor corporation 2380 bering drive san jose, california 95131 1-800-435-2336 fax (408) 435-1100 http://www.pericom.com 0.25 0.20 .025 bsc 0.635 .008 .008 .016 0-8? 0.20 0.40 .110 2.79 .010 gauge plane .291 .299 x.xx x.xx denotes dimensions in millimeters 7.39 7.59 .396 .416 10.06 10.56 .02 .04 0.51 1.01 .015 .025 0.381 0.635 .720 .730 18.29 18.54 .008 .0135 0.20 0.34 1 56 x 45? nom. max

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